Update mlir-aie and use mlir-aie utils when possible - #153
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v1.4.0 carries two breaking changes that the pinned v1.3.5.dev20 predates, so the version bump alone does not build. mlir-aie #3387 reworked the IRON Runtime into a callback body. Runtime() plus 'with rt.sequence(...)' is gone; the constructor now takes (seq_fn, fn_args), fill/drain moved onto the ObjectFifo handle, workers moved to Program(workers=), task_group()/finish_task_group() became TaskGroup()/tg.finish(), set_barrier() became barrier.set(), inline_ops() became a direct call, enable_trace() moved to Program and sync_parameters() to module scope. The per-transfer tile= argument is now bound on .prod()/.cons(), since placement is a property of the handle. mlir-aie #3364 unified aiecc's output selection under --get-<name>, removing --aie-generate-xclbin, --aie-generate-npu-insts and --no-compile-host. Asking only for the insts is what --no-compile used to mean, so that flag goes away rather than being renamed. Two spots needed more than a rename. gemm returns tensor access patterns that are recorded while the sequence body runs, and the body now runs at resolve_program() rather than at construction, so the program is resolved before the taps are read. mem_copy guarded rt.start on 'not bypass', which becomes a conditional workers= argument. Verified on Strix (npu2): the axpy suite passes 20/20 on device.
…0.2026081401 Builds on #145's v1.4.0 migration. Fixes further upstream breaking changes: - aiecc flipped its Peano/Chess default; --no-xchesscc/--no-xbridge no longer exist, so drop them (Peano is now the implicit default) - XRTTensor's residency tracking was reworked into a Storage/coherence-map model; XRTSubBuffer now shares its parent's _storage instead of bootstrapping incompatible state - drop --dynamic-objFifos everywhere it was passed (default upstream now) Also fixes iron/operators/__init__.py unconditionally importing the stream-dse-backed operator, which broke its documented self-skip behavior when onnx/stream-dse aren't installed. Verified: 146/146 fast + 2830/2830 extensive operator tests pass on NPU2 hardware (some extensive failures under -n auto were pre-existing xdist build-directory races, confirmed passing when rerun serially). Co-Authored-By: Claude <noreply@anthropic.com>
mlir-aie's nightly (1.4.2.dev12) added a first-class subview() API backed by a shared storage/coherence map between a view and its parent. This directly supersedes XRTSubBuffer, which existed only because that capability didn't exist upstream (per its own TODO). Deleting it also fixes a real bug it had: XRTSubBuffer.to() always resynced the *entire* parent buffer, which could clobber a sibling sub-view whose fresh device data hadn't been read back yet. subview()'s shared coherence map tracks dirtiness per byte range instead, so each view's .to() only moves what it needs to. Converts all six call sites (iron/common/sequence.py, and four in llama_npu.py) from XRTSubBuffer(...)/XRTSubBuffer.from_parent(...) to parent.subview(offset_bytes, shape, dtype), then deletes the class. Verified: 146/146 fast + 2830/2830 extensive operator tests pass on NPU2 hardware. llama_npu.py's call sites are syntax/import-checked only; no model weights available locally to run it end-to-end. Co-Authored-By: Claude <noreply@anthropic.com>
…_arch() get_kernel_dir() reimplemented the device-arch-to-kernel-dir-string mapping that mlir-aie's aie.utils.compile.utils.resolve_target_arch() now provides. Keep our own no-arg auto-detect default (resolve_target_arch(None) returns "aie2" unconditionally rather than checking the current device, which would silently regress every no-arg call site on NPU2 hardware), but delegate the actual device->arch-string logic once a concrete device is known. Verified: 2830/2830 operator tests pass on NPU2 hardware. Co-Authored-By: Claude <noreply@anthropic.com>
Replaces the hand-built clang++/xchesscc invocation in KernelCompilationRule.compile() with aie.utils.compile.utils's compile_cxx_core_function(), wrapped in PythonCallbackCompilationCommand (which exists precisely for this: an arbitrary Python callable deferred into the same plan/execute contract as ShellCompilationCommand). This looked architecturally blocked at first (IRON's compile() methods return commands for a separate execute() step, while upstream's function runs synchronously), but IRON's execute() is already fully sequential in Python -- the only real parallelism is aiecc's own internal -j flag inside a single invocation, which is unaffected here since this rule only compiles individual kernel objects, not the aiecc/xclbin step. Nothing is lost by switching to a blocking call under a deferred wrapper. peano_dir/mlir_aie_dir were already always sourced from aie.utils.config.peano_install_dir()/root_path() (iron/common/context.py), the same config module the upstream function reads internally, so there's no override capability to lose. xchesscc_wrapper resolves via `shutil.which` upstream instead of an absolute path IRON constructed itself, but the wheel install puts it on PATH (ironenv/bin/xchesscc_wrapper), so this is a non-issue in the standard install. -Wno-missing-template-arg-list-after-template-kw is kept as an IRON-side extra flag (Peano-only, matching prior behavior) since it's specific to our kernel sources and upstream's default flag list doesn't include it. Symbol renaming/prefixing for operator fusion (_rename_symbols/ _prefix_symbols) stays IRON-side; upstream has no equivalent multi-symbol bulk-prefix operation. Verified: 146/146 fast + 2830/2830 extensive operator tests pass on NPU2 hardware, including a from-scratch rebuild (rm -rf build/) to exercise every kernel compile through the new path. The use_chess=True path is unexercised by any test (also true before this change). Co-Authored-By: Claude <noreply@anthropic.com>
Replaces the hand-built aiecc invocation in AieccXclbinInstsCompilationRule and AieccFullElfCompilationRule with aie.utils.compile.utils's compile_mlir_module(), wrapped in PythonCallbackCompilationCommand (same pattern as the prior KernelCompilationRule change). Two real gaps had to be worked around, not just papered over: - compile_mlir_module() always names its own copy of the MLIR source "aie.mlir" inside a work_dir it controls, rather than accepting an existing file path. IRON's build previously kept every artifact's .mlir file (and aiecc's ".prj" companion) at a distinctive flat filename in one shared build/ directory. Introduced _aiecc_work_dir(), giving each MLIR source its own "<name>.mlir.d/" subdirectory, and updated the one place that depended on the old "<name>.mlir.prj" convention (OperatorSequence's params.txt lookup in sequence.py) to derive the new path the same way. - aiecc resolves an MLIR module's relative kernel-object references (e.g. link_with = "axpy.o") against that work_dir, not against the flat build_dir where KernelCompilationRule/ArchiveCompilationRule actually produced them. Added _link_build_outputs_into() to symlink the build directory's existing outputs into each artifact's work_dir before compiling, rather than reworking where kernel objects get built. Known, accepted regression: compile_mlir_module() resolves aiecc via aie.utils.compile.utils's own config.aiecc_path(), which does not honor the AIECC_PATH env var IRON previously supported for pointing a build at a locally-built aiecc without reinstalling the wheel. No test exercises this, but it's a real dev-workflow feature being dropped, not just an implementation detail. peano_dir/mlir_aie_dir/build_dir are no longer threaded into AieccCompilationRule's constructor (dead after this change), simplifying the context.py call sites accordingly. Verified: 146/146 fast + 2830/2830 extensive operator tests pass on NPU2 hardware, from a clean build/ (rm -rf) to exercise every aiecc invocation through the new path, and again from a warm cache. Co-Authored-By: Claude <noreply@anthropic.com>
Bumps to the latest nightly wheels as of 2026-08-20 (mlir-aie 1.4.2.dev16+g7e00b57, llvm-aie 22.0.0.2026082001+84660bc3), up from 1.4.2.dev12 / 2026081401. Verified: 725/750 fast (non-extensive) operator/infra tests pass on NPU2 hardware. The 25 failures are the pre-existing fused-dispatch aiebu-asm gap (XRT 2.20.0 lacks aiebu-asm on PATH; needs >=2.21), unrelated to this bump. Co-Authored-By: Claude <noreply@anthropic.com>
SequenceFullELFCallable.params looked for params.txt under a nested "aie.mlir.prj" subdirectory of the aiecc work dir. That convention matched aiecc's *default* project-dir naming (used when --tmpdir is omitted), but compile_mlir_module() (introduced in 4f50d26) always passes --tmpdir explicitly, in which case aiecc treats that directory as the project dir itself rather than nesting another ".prj" folder under it. Confirmed against a fresh build/<name>.mlir.d/ directory: aie.mlir, bif_main.bif, cdo_main/ all land directly in it, not in a nested aie.mlir.prj/. This is the only caller of ParameterScratchpad in the tree, and only exercised by the llama_3.2_1b decode path (cache_offset/softmax_vector_size), so it wasn't caught by the 146/146 fast + 2830/2830 extensive operator runs. Co-Authored-By: Claude <noreply@anthropic.com>
3cded00 replaced IRON's hand-rolled XRTSubBuffer with upstream NpuTensor.subview() for the XRT dispatch path (SequenceXclbinCallable), but left one spot behind: SequenceReferenceCallable's pure-CPU path still built its sliced sub-buffers by hand, constructing a bare CPUOnlyTensor and overwriting its _data/_shape fields directly with a numpy slice. CPUOnlyTensor is itself an NpuTensor subclass and already implements _subview(), so this was reimplementing, by hand, what parent.subview(...) already does for this backend -- minus the 64-byte coherence-granule alignment check subview() enforces "for every backend, including the CPU-only one that has no coherence concern of its own... so a layout validated against the test backend stays valid on a device" (per its docstring). That check previously only fired on the XRT path; a layout that would fail on hardware could silently pass under dispatch="reference". Once both _make_subbuffer overrides just called .subview() with the same arguments, the hook itself stopped pulling weight: inlined the .subview() call directly into the shared _PerBufferCallable._resolve_buffer and deleted _make_subbuffer from both subclasses and the base class. Only _make_buffer (XRTTensor vs. CPUOnlyTensor construction) remains as the per-backend hook, which is genuine backend variation. fuse_mlir() (iron/common/compilation/sequence.py) is out of scope here: it generates memref.subview/reinterpret_cast MLIR directly to implement IRON's own operator-fusion runlist calling convention, which has no upstream equivalent to delegate to. dispatch="reference" had no test coverage at all in iron/tests/infrastructure/sequence.py before this change, and specifically none exercising slice_info/explicit_buffer_sizes resolution on the CPU backend -- the only real caller of sliced buffers (llama's per-head attention slicing) only runs the XRT path. Added test_reference_dispatch_resolves_sliced_buffer to close that gap. Verified: 755/755 fast (non-extensive) operator/infra/application tests pass on NPU2 hardware (24 llama tests skip, pre-existing XRT 2.20.0 gap), including the new test and the full iron/tests/infrastructure/sequence.py suite (80/80). Extensive suite not re-run: its markers cover per-operator kernel parameter sweeps, orthogonal to this sequence-dispatch change. Co-Authored-By: Claude <noreply@anthropic.com>
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CI Test Resultsac74085 (2026_08_24_18_10_18) IRON - CI SummarySmalliron/operators/axpy
iron/operators/dequant
iron/operators/elementwise_add
iron/operators/elementwise_mul
iron/operators/gelu
iron/operators/gemm
iron/operators/gemv
iron/operators/layer_norm
iron/operators/leaky_relu
iron/operators/mem_copy
iron/operators/relu
iron/operators/rms_norm
iron/operators/rope
iron/operators/sigmoid
iron/operators/silu
iron/operators/softmax
iron/operators/swiglu_decode
iron/operators/swiglu_prefill
iron/operators/tanh
iron/operators/transpose
Phoenix - SmallIRONTested on iron/operators/axpy
iron/operators/dequant
iron/operators/elementwise_add
iron/operators/elementwise_mul
iron/operators/gelu
iron/operators/gemm
iron/operators/gemv
iron/operators/layer_norm
iron/operators/leaky_relu
iron/operators/mem_copy
iron/operators/relu
iron/operators/rms_norm
iron/operators/rope
iron/operators/sigmoid
iron/operators/silu
iron/operators/softmax
iron/operators/swiglu_decode
iron/operators/swiglu_prefill
iron/operators/tanh
iron/operators/transpose
Trends: IRON Trendsiron/operators/axpytest_axpy[input_length_2048-num_aie_columns_1-tile_size_2048-scalar_factor_3.0]
test_axpy[input_length_2048-num_aie_columns_2-tile_size_1024-scalar_factor_3.0]
test_axpy[input_length_2048-num_aie_columns_4-tile_size_512-scalar_factor_3.0]
iron/operators/dequanttest_dequant[input_length_2048-num_aie_columns_1-num_channels_1-tile_size_2048-group_size_32]
test_dequant[input_length_2048-num_aie_columns_1-num_channels_2-tile_size_1024-group_size_32]
test_dequant[input_length_2048-num_aie_columns_2-num_channels_1-tile_size_1024-group_size_32]
test_dequant[input_length_2048-num_aie_columns_2-num_channels_2-tile_size_512-group_size_32]
test_dequant[input_length_2048-num_aie_columns_4-num_channels_1-tile_size_512-group_size_32]
test_dequant[input_length_2048-num_aie_columns_4-num_channels_2-tile_size_256-group_size_32]
iron/operators/elementwise_addtest_elementwise_add[input_length_2048-num_aie_columns_1-tile_size_2048]
test_elementwise_add[input_length_2048-num_aie_columns_2-tile_size_1024]
test_elementwise_add[input_length_2048-num_aie_columns_4-tile_size_512]
iron/operators/elementwise_multest_elementwise_mul[input_length_2048-num_aie_columns_1-tile_size_2048]
test_elementwise_mul[input_length_2048-num_aie_columns_2-tile_size_1024]
test_elementwise_mul[input_length_2048-num_aie_columns_4-tile_size_512]
iron/operators/gelutest_gelu[input_length_2048-num_aie_columns_1-num_channels_1-tile_size_2048]
test_gelu[input_length_2048-num_aie_columns_1-num_channels_2-tile_size_1024]
test_gelu[input_length_2048-num_aie_columns_2-num_channels_1-tile_size_1024]
test_gelu[input_length_2048-num_aie_columns_2-num_channels_2-tile_size_512]
test_gelu[input_length_2048-num_aie_columns_4-num_channels_1-tile_size_512]
test_gelu[input_length_2048-num_aie_columns_4-num_channels_2-tile_size_256]
iron/operators/gemmtest_gemm[M_192-K_384-N_64-num_aie_columns_4-b_col_maj_False-c_col_maj_False-m_48-k_96-n_16-trace_size_0-partition_N_1]
test_gemm[M_192-K_384-N_64-num_aie_columns_4-b_col_maj_True-c_col_maj_True-m_48-k_96-n_16-trace_size_0-partition_N_1]
test_gemm[M_2048-K_2048-N_2048-num_aie_columns_1-b_col_maj_False-c_col_maj_False-m_64-k_64-n_64-trace_size_0-partition_N_1]
test_gemm[M_2048-K_2048-N_2048-num_aie_columns_2-b_col_maj_True-c_col_maj_False-m_64-k_64-n_64-trace_size_0-partition_N_1]
test_gemm[M_384-K_1536-N_1792-num_aie_columns_4-b_col_maj_True-c_col_maj_False-m_32-k_48-n_64-trace_size_0-partition_N_1]
test_gemm[M_64-K_512-N_256-num_aie_columns_4-b_col_maj_True-c_col_maj_False-m_16-k_64-n_64-trace_size_0-partition_N_4]
iron/operators/gemvtest_gemv[M_128-K_128-num_aie_columns_1-tile_size_input_32-tile_size_output_128]
test_gemv[M_2048-K_8192-num_aie_columns_1-tile_size_input_1-tile_size_output_2048]
test_gemv[M_2048-K_8192-num_aie_columns_2-tile_size_input_1-tile_size_output_1024]
test_gemv[M_2048-K_8192-num_aie_columns_4-tile_size_input_1-tile_size_output_512]
test_gemv[M_8192-K_2048-num_aie_columns_1-tile_size_input_4-tile_size_output_1024]
test_gemv[M_8192-K_2048-num_aie_columns_2-tile_size_input_4-tile_size_output_1024]
test_gemv[M_8192-K_2048-num_aie_columns_4-tile_size_input_4-tile_size_output_1024]
test_gemv_batched[M_1024-K_1024-num_aie_columns_1-tile_size_input_1-tile_size_output_64-num_batches_2]
test_gemv_batched[M_1026-K_64-num_aie_columns_1-tile_size_input_1-tile_size_output_2-num_batches_2]
test_gemv_batched[M_256-K_128-num_aie_columns_1-tile_size_input_1-tile_size_output_256-num_batches_4]
test_gemv_batched[M_64-K_1536-num_aie_columns_1-tile_size_input_1-tile_size_output_64-num_batches_8]
test_gemv_gelu[M_128-K_128-num_aie_columns_1-tile_size_input_32-tile_size_output_128]No metrics available. test_gemv_gelu[M_2048-K_8192-num_aie_columns_1-tile_size_input_1-tile_size_output_2048]No metrics available. test_gemv_gelu[M_8192-K_2048-num_aie_columns_1-tile_size_input_4-tile_size_output_1024]No metrics available. iron/operators/layer_normtest_layer_norm[input_length_2048-num_aie_columns_1-num_channels_1-tile_size_2048]
test_layer_norm[input_length_2048-num_aie_columns_1-num_channels_2-tile_size_1024]
test_layer_norm[input_length_2048-num_aie_columns_2-num_channels_1-tile_size_1024]
test_layer_norm[input_length_2048-num_aie_columns_2-num_channels_2-tile_size_512]
test_layer_norm[input_length_2048-num_aie_columns_4-num_channels_1-tile_size_512]
test_layer_norm[input_length_2048-num_aie_columns_4-num_channels_2-tile_size_256]
iron/operators/leaky_relutest_leaky_relu[input_length_2048-num_aie_columns_1-num_channels_1-tile_size_2048-alpha_0.01]
test_leaky_relu[input_length_2048-num_aie_columns_1-num_channels_1-tile_size_2048-alpha_0.1]
test_leaky_relu[input_length_2048-num_aie_columns_1-num_channels_1-tile_size_2048-alpha_0.25]
test_leaky_relu[input_length_2048-num_aie_columns_1-num_channels_2-tile_size_1024-alpha_0.01]
test_leaky_relu[input_length_2048-num_aie_columns_2-num_channels_1-tile_size_1024-alpha_0.01]
test_leaky_relu[input_length_2048-num_aie_columns_2-num_channels_2-tile_size_512-alpha_0.01]
test_leaky_relu[input_length_2048-num_aie_columns_4-num_channels_1-tile_size_512-alpha_0.01]
test_leaky_relu[input_length_2048-num_aie_columns_4-num_channels_2-tile_size_256-alpha_0.01]
iron/operators/mem_copytest_mem_copy[input_length_2048-num_cores_1-num_channels_1-bypass_False-tile_size_2048]
test_mem_copy[input_length_2048-num_cores_2-num_channels_1-bypass_False-tile_size_1024]
test_mem_copy[input_length_2048-num_cores_2-num_channels_2-bypass_False-tile_size_1024]
test_mem_copy[input_length_2048-num_cores_4-num_channels_1-bypass_False-tile_size_512]
test_mem_copy[input_length_2048-num_cores_4-num_channels_2-bypass_False-tile_size_512]
test_mem_copy[input_length_2048-num_cores_8-num_channels_2-bypass_False-tile_size_256]
iron/operators/rms_normtest_rms_norm[input_length_2048-num_aie_columns_1-num_channels_1-tile_size_2048-weighted_False]
test_rms_norm[input_length_2048-num_aie_columns_1-num_channels_1-tile_size_2048-weighted_True]
test_rms_norm[input_length_2048-num_aie_columns_1-num_channels_2-tile_size_1024-weighted_False]
test_rms_norm[input_length_2048-num_aie_columns_1-num_channels_2-tile_size_1024-weighted_True]
test_rms_norm[input_length_2048-num_aie_columns_2-num_channels_1-tile_size_1024-weighted_False]
test_rms_norm[input_length_2048-num_aie_columns_2-num_channels_1-tile_size_1024-weighted_True]
test_rms_norm[input_length_2048-num_aie_columns_2-num_channels_2-tile_size_512-weighted_False]
test_rms_norm[input_length_2048-num_aie_columns_2-num_channels_2-tile_size_512-weighted_True]
test_rms_norm[input_length_2048-num_aie_columns_4-num_channels_1-tile_size_512-weighted_False]
test_rms_norm[input_length_2048-num_aie_columns_4-num_channels_1-tile_size_512-weighted_True]
test_rms_norm[input_length_2048-num_aie_columns_4-num_channels_2-tile_size_256-weighted_False]
iron/operators/ropetest_rope[rows_32-cols_512-angle_rows_32-aie_columns_1-method_type_0]
test_rope[rows_32-cols_512-angle_rows_32-aie_columns_2-method_type_0]
test_rope[rows_32-cols_512-angle_rows_32-aie_columns_4-method_type_0]
test_rope[rows_32-cols_512-angle_rows_8-aie_columns_1-method_type_0]
test_rope[rows_32-cols_512-angle_rows_8-aie_columns_2-method_type_0]
test_rope[rows_32-cols_512-angle_rows_8-aie_columns_4-method_type_0]
iron/operators/softmaxtest_softmax[input_length_32768-num_aie_columns_2-num_channels_2-tile_size_1024]
test_softmax[input_length_32768-num_aie_columns_2-num_channels_2-tile_size_2048]
test_softmax[input_length_32768-num_aie_columns_2-num_channels_2-tile_size_512]
iron/operators/swiglu_decodetest_swiglu_decode[embedding_dim_1024-hidden_dim_3584]
test_swiglu_decode[embedding_dim_2048-hidden_dim_2048]
iron/operators/swiglu_prefilltest_swiglu_prefill[seq_len_256-embedding_dim_2048-hidden_dim_2048-prio_accuracy_False]
iron/operators/transposetest_transpose[M_2048-N_64-aie_columns_1-channels_1-m_64-n_64-s_8-num_batches_1]
test_transpose[M_2048-N_64-aie_columns_1-channels_1-m_64-n_64-s_8-num_batches_2]
test_transpose[M_2048-N_64-aie_columns_1-channels_1-m_64-n_64-s_8]
test_transpose[M_2048-N_64-aie_columns_1-channels_2-m_64-n_64-s_8-num_batches_1]
test_transpose[M_2048-N_64-aie_columns_1-channels_2-m_64-n_64-s_8]
Phoenix - ExamplesIRONTested on Trends: IRON Trends |
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@copilot Can you update this PR to use the latest nightly mlir-aie, update with conflict solutions along the way, and then continue the main purpose of this PR, which is to deduplicate python infrastructure between mlir-aie and IRON whenever possible? |
# Conflicts: # iron/common/compilation/base.py # iron/common/sequence.py # iron/common/utils.py # iron/operators/__init__.py # iron/operators/gemm/design.py # iron/operators/mem_copy/design.py # iron/operators/mha/design.py # iron/operators/swiglu_prefill_stream/op.py # requirements.txt Co-authored-by: hunhoffe <54562339+hunhoffe@users.noreply.github.com>
Co-authored-by: hunhoffe <54562339+hunhoffe@users.noreply.github.com>
Co-authored-by: hunhoffe <54562339+hunhoffe@users.noreply.github.com>
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Updated in 5926b93, 0e3905c, and cfe3918: merged current 26 targeted tests pass; formatting, REUSE, secret scans, CodeQL, and the independent final review are clean. Torch-dependent tests remain skipped because its download is blocked. Compilation reached final packaging, blocked by missing |
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@copilot can you help fix CI errors? |
Co-authored-by: hunhoffe <54562339+hunhoffe@users.noreply.github.com>
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Fixed in 18875f1. Both failed lint runs reported the same Black formatting issue in the sliced-reference test. Also fixed the logged apt permission error by using Full Black, clang-format, and REUSE checks pass locally; CodeQL and secret scans are clean, and independent review found no issues. New CI runs show |
hunhoffe
commented
Sep 17, 2026
| - name: Install dependencies | ||
| run: | | ||
| apt-get update && apt-get install -y clang-format | ||
| sudo apt-get update |
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There was a problem hiding this comment.
This worked in the past, why was there a permission error now?
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There was a problem hiding this comment.
It wasn’t new—I checked the successful devel run from September 16, and it already logged the identical /var/lib/apt/lists/lock ... Permission denied error.
The workflow appeared to work because:
apt-get updatewas the left side of&&, so Bash’s-edid not exit when it failed; the install was skipped.- The following
pip installsucceeded, making the step green. - clang-format was already available on the runner, so the C++ check passed anyway.
My earlier explanation should have distinguished this hidden pre-existing error from the actual PR failure, which was Black formatting. sudo makes the apt commands work as intended, and separate lines ensure failures aren’t masked. Both latest lint runs now pass; no further code changes were needed.
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@copilot can you address my review? |
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Answered the review thread with evidence from yesterday’s successful |
hunhoffe
marked this pull request as ready for review
September 17, 2026 18:10
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@copilot can you help me write a concise and accurate PR body description? |
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Suggested body, based on the current diff against ## Summary
Update mlir-aie to `1.4.4.dev4+g20a9c2f` and Peano to `22.0.0.2026091701+773413fb`, and reduce duplicated Python infrastructure:
- Share upstream `NpuTensor.subview()` handling across CPU and XRT sequence dispatch, keeping reference inputs CPU-resident.
- Use upstream `run_iters()` for benchmark warmup and NPU timing.
- Read trace buffers through the tensor NumPy API instead of round-tripping through torch.
- Add regression coverage for sliced buffers, timing, and trace data preservation.
- Fix lint dependency installation permissions and Python formatting.
## PR Merge Checklist
1. [ ] The PR includes the latest `devel` changes and targets `devel`.
2. [ ] The PR has been reviewed and approved.
3. [ ] All checks are passing. |
andrej
approved these changes
Sep 17, 2026
andrej
approved these changes
Sep 17, 2026
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Update mlir-aie to
1.4.4.dev4+g20a9c2fand Peano to22.0.0.2026091701+773413fb, and reduce duplicated Python infrastructure:NpuTensor.subview()handling across CPU and XRT sequence dispatch, keeping reference inputs CPU-resident.run_iters()for benchmark warmup and NPU timing.PR Merge Checklist
develcommit and pointing todevel.