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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

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  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

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  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.9k 306

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

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  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

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  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 748 180

Repositories

Showing 10 of 122 repositories
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw's past year of commit activity
    Rust 168 Apache-2.0 128 240 (8 issues need help) 76 Updated Sep 16, 2026
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw's past year of commit activity
    Rust 38 Apache-2.0 86 159 (5 issues need help) 84 Updated Sep 16, 2026
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss's past year of commit activity
    SystemVerilog 52 Apache-2.0 61 96 38 Updated Sep 16, 2026
  • Surelog Public

    SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    chipsalliance/Surelog's past year of commit activity
    C++ 475 Apache-2.0 90 47 (2 issues need help) 0 Updated Sep 16, 2026
  • UHDM Public

    Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    chipsalliance/UHDM's past year of commit activity
    C++ 269 Apache-2.0 48 14 0 Updated Sep 16, 2026
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl's past year of commit activity
    SystemVerilog 155 Apache-2.0 107 115 (2 issues need help) 40 Updated Sep 16, 2026
  • Caliptra Public

    Caliptra IP and firmware for integrated Root of Trust block

    chipsalliance/Caliptra's past year of commit activity
    473 Apache-2.0 78 121 16 Updated Sep 16, 2026
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator's past year of commit activity
    SystemVerilog 44 912 0 0 Updated Sep 15, 2026
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests's past year of commit activity
    SystemVerilog 394 ISC 103 47 (4 issues need help) 37 Updated Sep 15, 2026
  • caliptra-SPDM-Responder-Validator Public
    chipsalliance/caliptra-SPDM-Responder-Validator's past year of commit activity
    C 0 BSD-3-Clause 3 0 3 Updated Sep 15, 2026
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