Issues

• bootargs is not supported in litex_term --images boot

  enjoy-digital/litex#2764 · Filter by author awariac opened on Nov 6, 2026

• LiteX JTAG server: slow register reads and silent binary data corruption

  answered-waiting-feedback
  enjoy-digital/litex#2635 · Filter by author VoidReg opened on Sep 27, 2026
  2

• Add ledwall to the "LiteX open-source projects" wiki page

  add-answer-to-wiki
  enjoy-digital/litex#2626 · Filter by author siegeld opened on Sep 20, 2026
  1

• BIOS netboot() has no PHY link wait or retry (fails at power-on); trellis_argdict inverts the ecppack compress default

  answered-waiting-feedback
  enjoy-digital/litex#2603 · Filter by author siegeld opened on Sep 16, 2026
  4

• CSRBank with more than paging//4 CSRs silently aliases into the next module's CSR page

  enjoy-digital/litex#2587 · Filter by author AUTHENSOR opened on Sep 10, 2026

• support cocotb+verilator for sim

  question
  enjoy-digital/litex#2380 · Filter by author DavisLiu1989 opened on Dec 5, 2025
  2

• How to support larger memory (>4GB) with VexiiRiscv in LiteX?

  bug?enhancementquestion
  enjoy-digital/litex#2363 · Filter by author looongbin opened on Nov 11, 2025
  13

• Can't load Linux on Microwatt and Litex Bios

  answered-waiting-feedbackbug?
  enjoy-digital/litex#2306 · Filter by author MojoJojo opened on Aug 10, 2025
  9

• The L2 cache of the VexiiRiscv CPU causes the BIOS to hang during startup on the ECP5 FPGA.

  bug?question
  enjoy-digital/litex#2304 · Filter by author leeguang517 opened on Aug 9, 2025

• add_video_framebuffer not configured to work with HyperRAM.

  enhancementquestion
  enjoy-digital/litex#2303 · Filter by author fIREmiNeR1 opened on Aug 4, 2025
  1

• How to pass defines to verilator/yosys

  enhancementquestion
  enjoy-digital/litex#2283 · Filter by author keesj opened on Jul 11, 2025
  1

• titaniumrgmii problem

  bug?
  enjoy-digital/litex#2262 · Filter by author cicamargoba opened on Jun 17, 2025
  2

• Vivado: user constraints added as EARLY get overriden by Xilinx IP xdc

  bug?enhancement
  enjoy-digital/litex#2245 · Filter by author enurseitov opened on May 14, 2025

• Converting Wishbone to riscv-steel custom bus

  new-featurequestion
  enjoy-digital/litex#2178 · Filter by author BMorgan1296 opened on Feb 7, 2025
  2

• Support SD cards in DDR50 mode

  enhancement
  enjoy-digital/litex#2177 · Filter by author machdyne opened on Feb 6, 2025
  1

• CVA6 + Nexys4 DDR - RAM access issues

  bug?question
  enjoy-digital/litex#2121 · Filter by author juanschroeder opened on Nov 8, 2024
  2

• RFC: Etherbone address detection

  enhancementquestion
  enjoy-digital/litex#2085 · Filter by author m-byte opened on Sep 28, 2024
  2

• [RFC] CSRBone or some MMIO debugging bridge

  enhancement
  enjoy-digital/litex#2002 · Filter by author FlyGoat opened on Jun 24, 2024

• Proposal: Generate csr offset header files

  enhancement
  enjoy-digital/litex#1979 · Filter by author AndrewD opened on Jun 4, 2024
  2

• RFC: refactor devicetree (DTS) generation (draft)

  enhancement
  enjoy-digital/litex#1960 · Filter by author AndrewD opened on May 21, 2024
  5

• liteeth linux driver performances

  enhancement
  enjoy-digital/litex#1924 · Filter by author Dolu1990 opened on Apr 13, 2024
  6

• Add example for embedding a LiteX SOC into Vivado project for Zynq

  enhancementguide
  enjoy-digital/litex#1910 · Filter by author benfre opened on Mar 29, 2024
  4

• Restrict bus crossbar access by region mode

  answered-waiting-feedbacknew-feature
  enjoy-digital/litex#1907 · Filter by author jdavidberger opened on Mar 20, 2024
  2

• Simulink-like design environment

  new-featurequestion
  enjoy-digital/litex#1766 · Filter by author davidbrochart opened on Sep 4, 2023
  4

• PSRAM backed framebuffer

  help-welcome :)new-featuresponsor-welcome :)
  enjoy-digital/litex#1620 · Filter by author suarezvictor opened on Feb 28, 2023