Fst Writer_03

.github/configs/mlc_config.json

@@ -19,7 +19,10 @@
       "pattern":"^https://docs.cocotb.org/en/stable/$"
     },
     {
-      "pattern":"^https://www.nandland.com"
+      "pattern": "^https://code\\.visualstudio\\.com/"
+    },
+    {
+      "pattern": "^https://www.nandland.com"
     },
     {
       "pattern":"^https://.*\\.fandom\\.com"

.github/workflows/build_devtool.yml

@@ -22,7 +22,7 @@ jobs:
           uses: flutter-actions/setup-flutter@v2
           with:
             channel: stable
-            version: 3.44.0
+            version: 3.47.2
 
         - name: Run Flutter Test
           run: tool/gh_actions/devtool/run_devtool_test.sh

.github/workflows/general.yml

@@ -170,7 +170,7 @@ jobs:
         uses: flutter-actions/setup-flutter@v2
         with:
           channel: stable
-          version: 3.44.0
+          version: 3.47.2
 
       - name: Run Flutter Test
         run: tool/gh_actions/devtool/run_devtool_test.sh

CHANGELOG.md

@@ -1,4 +1,9 @@
 
+## Next Release
+
+- Exposed the shared `rohd_source_navigator` code used by `rohd-schematic-viewer` as a standalone pub.dev package.
+- Corrected the ROHD dependency in `rohd_devtools_widgets` from `^0.6.9` to `^0.6.11` to reflect the minimum compatible ROHD version.
+
 ## 0.6.11
 
 - Added `NetlistSynthesizer` for generating JSON netlists, with configurable synthesis passes, validation, and hierarchy support (<https://github.com/intel/rohd/pull/675>).
@@ -14,6 +19,24 @@
 - Improved generated SystemVerilog to inline packed `Logic.assignSubset` connections into submodule inputs (<https://github.com/intel/rohd/pull/711>).
 - Fixed a bug where isolated bit drivers could be lost beside collapsed ranges (<https://github.com/intel/rohd/pull/711>).
 
+- Added the `ModuleService` API for module-scoped generation, capture, and
+  inspection services. `ModuleServices` registers and looks up services for a
+  built module hierarchy, and `hierarchyJson` exposes its hierarchy as JSON.
+- Added `ArtifactProducingService` and `ModuleServiceArtifact` for
+  transport-neutral output. Artifact-producing services default
+  `outputDirectory` to the current directory and `outputBaseName` to the
+  module definition name, and expose named, media-typed byte streams without
+  requiring filesystem output.
+- Added `SystemVerilogService` for configured SystemVerilog synthesis,
+  in-memory source output, artifact inspection, and explicit directory writes.
+  Added `WaveformService` for in-memory waveform capture with optional file
+  writing through `writeToFile`.
+- Added legacy-compatible `Module.dumpSystemVerilog` and `Module.dumpWaves`
+  convenience methods. `dumpSystemVerilog()` returns simple in-memory output;
+  `dumpWaves()` provides standard VCD capture as the replacement for
+  `WaveDumper`. `WaveDumper` and `generateSynth` are deprecated in favor of
+  these `Module` methods.
+
 ## 0.6.10
 
 - Improved `Logic.replicate(1)` and same-width `signExtend` to return the original signal, eliminating redundant replication modules and generated SystemVerilog (<https://github.com/intel/rohd/pull/689>).

CONTRIBUTING.md

@@ -6,7 +6,7 @@ Anyone interested in participating in ROHD is more than welcome to help!
 
 ## Code of Conduct
 
-ROHD adopts the [Contributor Covenant](https://www.contributor-covenant.org/) v2.1 for the code of conduct. It can be accessed [here](CODE_OF_CONDUCT.md).
+ROHD adopts the [Contributor Covenant](https://www.contributor-covenant.org/) v2.1 for the  [Code of Conduct](CODE_OF_CONDUCT.md).
 
 ## Getting Help
 
@@ -126,7 +126,7 @@ Please include the SPDX tag near the top of any new files you create:
 Here is an example of a recommended file header template:
 
 ```dart
-// Copyright (C) 2021-2023 Intel Corporation
+// Copyright (C) 2021-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // example.dart

analysis_options.yaml

@@ -10,6 +10,7 @@ analyzer:
     - doc/tutorials/chapter_9/rohd_vf_example
     - packages/rohd_devtools_widgets
     - packages/rohd_hierarchy
+    - packages/rohd_source_navigator
     - packages/rohd_waveform
     - reviews/**
     - rohd_devtools_extension

benchmark/many_submodules_benchmark.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2024 Intel Corporation
+// Copyright (C) 2024-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // many_submodules_benchmark.dart
@@ -33,7 +33,7 @@ class ManySubmodulesBenchmark extends AsyncBenchmarkBase {
   Future<void> run() async {
     final dut = ManySubmodulesModule(Logic(), numSubModules: 10000);
     await dut.build();
-    dut.generateSynth();
+    dut.dumpSystemVerilog();
   }
 }
 

benchmark/wave_dump_benchmark.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // wave_dump_benchmark.dart
@@ -56,7 +56,7 @@ class WaveDumpBenchmark extends AsyncBenchmarkBase {
     _mod = _ModuleToDump(Logic(), _clk);
     await _mod.build();
 
-    WaveDumper(_mod, outputPath: _vcdTemporaryPath);
+    _mod.dumpWaves(outputPath: _vcdTemporaryPath);
 
     await Simulator.run();
 

doc/releases.md

@@ -18,13 +18,15 @@ released, not a repository-wide version.
 | [rohd_hierarchy](../packages/rohd_hierarchy) | Shared hierarchy models, addressing, adapters, and search. | Independent pub.dev package; `dart pub publish` from its directory. | Its own `pubspec.yaml`. | Tag `rohd_hierarchy-v<version>`; release **rohd_hierarchy v<version>**. |
 | [rohd_waveform](../packages/rohd_waveform) | Shared waveform models and data services. | Independent pub.dev package; `dart pub publish` from its directory. | Its own `pubspec.yaml`. | Tag `rohd_waveform-v<version>`; release **rohd_waveform v<version>**. |
 | [rohd_devtools_widgets](../packages/rohd_devtools_widgets) | Reusable Flutter controls and utilities for debug viewers. | Independent pub.dev package; `flutter pub publish` from its directory. | Its own `pubspec.yaml`. | Tag `rohd_devtools_widgets-v<version>`; release **rohd_devtools_widgets v<version>**. |
+| [rohd_source_navigator](../packages/rohd_source_navigator) | Shared FLC data models and source-navigation utilities for debug viewers. | Independent pub.dev package; `dart pub publish` from its directory. | Its own `pubspec.yaml`. | Tag `rohd_source_navigator-v<version>`; release **rohd_source_navigator v<version>**. |
 | [ROHD DevTools application](../rohd_devtools_extension) | Interactive hardware debug UI embedded in Dart DevTools. | Flutter web build produced by CI and bundled under `extension/devtools` in the ROHD pub.dev package; the application itself is not published to pub.dev. | Tracked by the containing ROHD release and the build's source/artifact commits, not an independent application release version. | Included in ROHD's tag and release notes; no separate release tag. The `artifacts` branch holds CI output, not an immutable release. |
 | [ROHD VS Code extension](../rohd_extension) | Editor snippets, completions, and cross-probe source navigation. | GitHub Actions builds and attaches a VSIX when its GitHub release is published; a maintainer tests and publishes that VSIX to the VS Code Marketplace separately. | `rohd_extension/package.json`. | Tag `rohd-vscode-v<version>`; release `ROHD VS Code v<version>`, with `rohd-vscode-v<version>.vsix` attached automatically. |
 
-The internal Dart source-navigation port in `rohd_extension/dart` uses
-`publish_to: none` and has no independent release or tag. The VS Code extension
-compiles its TypeScript implementation, not the Dart port. Tutorial applications
-are also not independently released packages.
+The source-navigation library lives in `packages/rohd_source_navigator`, alongside
+the other independently published libraries. Git dependencies following the move
+must use the new package path; older pinned commits retain `rohd_extension/dart`.
+The VS Code extension still compiles its separate TypeScript implementation.
+Tutorial applications are not independently released packages.
 
 ## GitHub Strategy
 
@@ -91,13 +93,15 @@ with a merge or rebase; the preparation PR itself does not need to be merged yet
    `Check rohd_devtools_widgets` jobs for dependency resolution, formatting,
    fatal-info analysis, and package tests. These run alongside the root checks
    and DevTools app job; documentation deployment waits for all of them.
+   Source navigator is not included in that matrix; run its local checks with
+   `tool/prepare_release.sh --run-tests rohd_source_navigator`.
    Preparation skips local test suites by default and does not query GitHub or
    verify CI status.
    Use `--run-tests` to repeat selected package suites locally. ROHD's local
    tests require Icarus Verilog; Verilator is required in CI and when
    `ROHD_REQUIRE_VERILATOR=1`.
 5. Run `tool/prepare_release.sh [--run-tests] [package ...]` on the preparation
-   branch from the repository root. No package names selects all four; explicit
+   branch from the repository root. No package names selects all five; explicit
    names select only those packages. Versions come from their manifests, not
    command-line arguments. It validates selected metadata before making changes,
    fetches `main` from `intel/rohd`, and requires that commit to be an ancestor
@@ -115,9 +119,10 @@ with a merge or rebase; the preparation PR itself does not need to be merged yet
    commit, tag, push, or upload anything. If a guard fails, incorporate the latest
    `main` or wait for its artifact workflow as appropriate, then rerun preparation.
 6. To inspect archives without preparing metadata, run
-   `tool/check_release.sh [package ...]`. Like preparation, it defaults to all four
+   `tool/check_release.sh [package ...]`. Like preparation, it defaults to all five
    packages and accepts explicit names: `rohd`, `rohd_hierarchy`, `rohd_waveform`,
-   and `rohd_devtools_widgets`. Each uses its existing version. The helper runs
+   `rohd_devtools_widgets`, and `rohd_source_navigator`. Each uses its existing
+   version. The helper runs
    `dart pub publish --dry-run` in each selected Dart package directory or
    `flutter pub publish --dry-run` for widgets. Review
    warnings, included files, and compressed archive sizes. For ROHD, first prepare
@@ -130,7 +135,7 @@ Preparation runs the following checks before invoking `tool/check_release.sh`:
 | Selected Package | Default Checks | Added With `--run-tests` |
 | --- | --- | --- |
 | `rohd` | `tool/run_checks.sh --skip-tests`: dependencies, formatting, analysis, API docs, and temporary-file checks; then `tool/package_vscode.sh` compiles and packages a temporary VSIX. | Simulator prerequisites and ROHD tests via `tool/run_checks.sh`. |
-| `rohd_hierarchy`, `rohd_waveform` | In each package directory: `dart pub get`, `dart format --output=none --set-exit-if-changed .`, then `dart analyze --fatal-infos`. | `dart test` in each selected package. |
+| `rohd_hierarchy`, `rohd_waveform`, `rohd_source_navigator` | In each package directory: `dart pub get`, `dart format --output=none --set-exit-if-changed .`, then `dart analyze --fatal-infos`. | `dart test` in each selected package. |
 | `rohd_devtools_widgets` | In its package directory: `flutter pub get`, `dart format --output=none --set-exit-if-changed .`, then `flutter analyze --fatal-infos`. | `flutter test` in the widgets package. |
 
 Artifact provenance verification and the DevTools installation smoke test always
@@ -155,10 +160,10 @@ separate DevTools application remain a separate step when its shared widgets cha
 Preparation examples (choose one):
 
 ```sh
-# All four packages, using each manifest's version; rely on CI for test suites:
+# All five packages, using each manifest's version; rely on CI for test suites:
 tool/prepare_release.sh
 
-# All four packages, also running their test suites locally:
+# All five packages, also running their test suites locally:
 tool/prepare_release.sh --run-tests
 
 # ROHD only:
@@ -172,6 +177,9 @@ tool/prepare_release.sh rohd rohd_hierarchy rohd_waveform
 
 # Only hierarchy and waveform:
 tool/prepare_release.sh rohd_hierarchy rohd_waveform
+
+# Only source navigator:
+tool/prepare_release.sh rohd_source_navigator
 ```
 
 Preparation requires Dart for YAML metadata parsing using the root package's
@@ -195,6 +203,7 @@ the selected dry runs:
 tool/check_release.sh --validate-only
 tool/check_release.sh --validate-only rohd_hierarchy rohd_waveform rohd_devtools_widgets
 tool/check_release.sh rohd_hierarchy rohd_waveform rohd_devtools_widgets
+tool/check_release.sh rohd_source_navigator
 ```
 
 `--validate-only` checks package names, manifest presence, and SDK availability.
@@ -237,6 +246,13 @@ dependencies determine ordering only when the required versions have not yet
 been published. Sharing a repository or source commit does not require a
 coordinated release.
 
+`rohd_source_navigator` has only hosted Dart dependencies and can be published
+independently of ROHD and the Flutter packages. Once its version is available on
+pub.dev, consumers such as the ROHD Schematic Viewer can replace their Git
+dependency with `rohd_source_navigator: ^0.1.0` and remove any Git override for
+that package. Existing Dart imports remain unchanged. See the
+[package README](../packages/rohd_source_navigator/README.md) for migration details.
+
 For each package, wait until its required dependencies are available on pub.dev,
 then validate from a clean disposable checkout of the release commit without
 local dependency overrides or reused path-based lockfiles. Remove that checkout's

doc/tutorials/chapter_1/01_setup_installation.md

@@ -162,7 +162,7 @@ Future<void> main({bool noPrint = false}) async {
 
   // Let's see what this module looks like as SystemVerilog, so we can pass it
   // to other tools.
-  final systemVerilogCode = counter.generateSynth();
+  final systemVerilogCode = counter.dumpSystemVerilog();
   if (!noPrint) {
     print(systemVerilogCode);
   }
@@ -175,7 +175,7 @@ Future<void> main({bool noPrint = false}) async {
 
   // Attach a waveform dumper so we can see what happens.
   if (!noPrint) {
-    WaveDumper(counter);
+    counter.dumpWaves();
   }
 
   // Drop reset at time 25.

doc/tutorials/chapter_2/helper.dart

@@ -13,7 +13,8 @@ import 'package:rohd/rohd.dart';
 
 Future<void> displaySystemVerilog(Module mod) async {
   await mod.build();
-  print('\nYour System Verilog Equivalent Code: \n ${mod.generateSynth()}');
+  print('\nYour System Verilog Equivalent Code: \n '
+      '${mod.dumpSystemVerilog()}');
 }
 
 class LogicInitialization extends Module {

doc/tutorials/chapter_3/answers/exercise_sv.dart

@@ -1,3 +1,12 @@
+// Copyright (C) 2023-2026 Intel Corporation
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// exercise_sv.dart
+// Chapter 3 SystemVerilog exercise answer.
+//
+// 2023 March 30
+// Author: Yao Jing Quek <yao.jing.quek@intel.com>
+
 import 'package:rohd/rohd.dart';
 import 'package:test/test.dart';
 import 'helper.dart';
@@ -33,7 +42,7 @@ void main() async {
   await fSub.build();
 
   // ignore: avoid_print - tutorial
-  print(fSub.generateSynth());
+  print(fSub.dumpSystemVerilog());
 
   test('should return 0 when a and b equal 1', () {
     a.put(1);

doc/tutorials/chapter_3/full_adder.dart

@@ -1,3 +1,12 @@
+// Copyright (C) 2023-2026 Intel Corporation
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// full_adder.dart
+// Chapter 3 full-adder tutorial example.
+//
+// 2023 March 3
+// Author: Yao Jing Quek <yao.jing.quek@intel.com>
+
 // ignore_for_file: avoid_print - tutorial
 
 import 'package:rohd/rohd.dart';
@@ -76,5 +85,5 @@ void main() async {
   final mod = FullAdderModule(a, b, cIn, faOps);
   await mod.build();
 
-  print(mod.generateSynth());
+  print(mod.dumpSystemVerilog());
 }

doc/tutorials/chapter_4/answers/exercise_1_sv.dart

@@ -1,3 +1,12 @@
+// Copyright (C) 2023-2026 Intel Corporation
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// exercise_1_sv.dart
+// Chapter 4 SystemVerilog exercise answer.
+//
+// 2023 April 11
+// Author: Yao Jing Quek <yao.jing.quek@intel.com>
+
 import 'package:rohd/rohd.dart';
 import 'package:test/test.dart';
 
@@ -10,7 +19,7 @@ void main() async {
   final mod = NBitAdder(a, b);
   await mod.build();
 
-  print(mod.generateSynth());
+  print(mod.dumpSystemVerilog());
 
   test('should return 255 when both inputs are added', () {
     a.put(127);

doc/tutorials/chapter_4/answers/exercise_2_sv.dart

@@ -1,3 +1,12 @@
+// Copyright (C) 2023-2026 Intel Corporation
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// exercise_2_sv.dart
+// Chapter 4 SystemVerilog exercise answer.
+//
+// 2023 April 11
+// Author: Yao Jing Quek <yao.jing.quek@intel.com>
+
 import 'package:rohd/rohd.dart';
 import 'package:test/test.dart';
 
@@ -9,7 +18,7 @@ void main() async {
 
   final mod = NBitSubtractor(a, b);
   await mod.build();
-  print(mod.generateSynth());
+  print(mod.dumpSystemVerilog());
 
   test('should return 5 when a is 25 and b is 20', () {
     a.put(25);

doc/tutorials/chapter_4/basic_generation_sv.dart

@@ -1,3 +1,12 @@
+// Copyright (C) 2023-2026 Intel Corporation
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// basic_generation_sv.dart
+// Chapter 4 basic SystemVerilog generation tutorial example.
+//
+// 2023 April 11
+// Author: Yao Jing Quek <yao.jing.quek@intel.com>
+
 import 'package:rohd/rohd.dart';
 import 'package:test/test.dart';
 
@@ -78,7 +87,7 @@ void main() async {
 
   await nbitAdder.build();
 
-  print(nbitAdder.generateSynth());
+  print(nbitAdder.dumpSystemVerilog());
 
   test('should return 10 when both inputs are 5.', () {
     a.put(5);

doc/tutorials/chapter_5/00_basic_modules.md

@@ -95,7 +95,7 @@ Do note that the `build()` method returns a `Future<void>`, not just `void`. Thi
 
 ## Converting ROHD Module to System Verilog RTL
 
-Next, we can see how extending your `Logic` to `Module` enables the generation of system Verilog code. Building on the previous example, we've made some slight modifications by adding `simModule.build()` and `simModule.generateSynth()`.
+Next, we can see how extending your `Logic` to `Module` enables the generation of system Verilog code. Building on the previous example, we've made some slight modifications by adding `simModule.build()` and `simModule.dumpSystemVerilog()`.
 
 ```dart
 void main() async {
@@ -106,15 +106,16 @@ void main() async {
     await simModule.build();
 
     // Print out system verilog code
-    print(simModule.generateSynth());
+    print(simModule.dumpSystemVerilog());
 
     test('should return input value.',
           () => expect(simModule.out.value.toInt(), equals(1)));
 
     // Add this to test on generate system verilog code
     test(
           'should generate system verilog code.',
-        () => expect(simModule.generateSynth(), contains('module SimpleModule(')));
+        () => expect(simModule.dumpSystemVerilog(),
+          contains('module SimpleModule(')));
 }
 ```