SDC Request #77

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1. DiyouS commented on Apr 16, 2026

   

   DiyouS

   on Apr 16, 2026

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   Unfortunately, we have not yet run synthesis on the design in the open-sourced PDK. We cannot open-source constraints for a commercial PDK.
   But there is no special constraint requirement for the design, except the fpu module (fpnew) may need retiming.
2. verilogdev commented on Jul 15, 2026

   

   verilogdev

   on Jul 15, 2026

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   Are there any clock frequency limitations for the design? Specifically, are there any minimum or maximum clock frequency constraints that the design must operate within?
3. verilogdev

   closed this as completedon Jul 15, 2026
4. verilogdev

   reopened this on Jul 15, 2026