[lhartmann]

AI disclaimer: Code generated by gemini/antigravity, tested on real hardware, human PR. Not sure what is the stance on AI coding, but I tried to keep existing code changes to a minimum.

Digilent Basys 2 is a legacy Spartan3e based board. It is legacy, and not supported by recent Xilinx tooling anymore (requres ISE, not Vivado). Regardless, it is still usable for learning Verilog.

There is an onboard AT90USB implementing JTAG and a Enhanced Parallel Port (EPP) connections to the FPGA. This was previously reverse engineered by Marcin Kościelnicki, who provided reference python implementations.

This PR ports the JTAG part of the interface to openFPGAloader.

$ openFPGALoader -b basys2 --detect                      
index 0:
        idcode 0x11c10093
        manufacturer xilinx
        family spartan3e
        model  xc3s100e
        irlength 6
index 1:
        idcode 0x5045093
        manufacturer xilinx
        family xcf
        model  xcf02s
        irlength 8

$ openFPGALoader -b basys2 --index-chain 0 build/test.bit   
Open file build/test.bit DONE
Parse file DONE
Load SRAM: [==================================================] 100.00%
Done

$ openFPGALoader -b basys2 --index-chain 1 -f build/test.bit
write to flash
Open file build/test.bit DONE
Parse file DONE
Erase flash DONE
Write PROM: [==================================================] 100.00%
Done

[trabucayre]

Sorry for the late to answer.
I have applied some additionnals commits to simplify a bit the code and to have something more coherent with others cable drivers.
But I haven't this cable to test for possible regression with new commits.
Thanks

[lhartmann]

It failed to write SRAM, but worked on flash. (A)I found 3 regressions:

• Bit->byte count conversion was incorrect when len was multiple of 8 and end==true.
• Partial byte alignment to LSB is done in hardware, so not necessary on software.
• TMS should be true when end is active, so JTAG exits SHIFT states.

Patched, and tested working for both SRAM and FLASH.

P.S.: Late? I have an open bug on KDE that is 12yo now. Thanks for your efforts, I really appreciate the software!

[trabucayre]

Sorry for the regression. I develop in blind mode here :)

I have applied a last commit to try to have a clean rx_ptr at each step (bits transfer and end transfer)

Thanks