[umarcor]

RHS Research PicoEVB Rev D, featuring a Xilinx Artix-7 XC7A50T-2CSG325C FPGA.
The board includes an integrated FTDI FT230X USB-to-JTAG interface which operates in bit-bang mode.

JTAG pin mapping:

• TMS: CTS
• TCK: TXD
• TDI: RXD
• TDO: RTS

VID:PID: 0403:6015

$ openFPGALoader -c ft231X --pins=RXD:RTS:TXD:CTS --detect
empty
Jtag probe limited to 3MHz
Jtag frequency : requested 6000000Hz -> real 3000000Hz
ret 0
index 0:
        idcode 0x362c093
        manufacturer xilinx
        family artix a7 50t
        model  xc7a50t
        irlength 6

Both bitstream loading and SPI flash programming were tested.

$ sudo openFPGALoader -c ft231X --pins=RXD:RTS:TXD:CTS PicoEVB_demo.bit
empty
Jtag probe limited to 3MHz
Jtag frequency : requested 6000000Hz -> real 3000000Hz
ret 0
Open file DONE
Parse file DONE
load program
Load SRAM: [==================================================] 100.00%
Done
Shift IR d5
ir: 1 isc_done 1 isc_ena 0 init 1 done 0
Register raw value: 0x501079fc
CRC Error       No CRC error
Part Secured    0x0
MMCM lock       0x1
DCI match       0x1
EOS             0x1
GTS CFG B       0x1
GWE             0x1
GHIGH B         0x1
MODE            0x1
INIT Complete   0x1
INIT B          0x1
Release Done    0x1
Done            0x1
ID Error        No ID error
DEC Error       0x0
XADC Over temp  0x0
STARTUP State   0x4
Reserved        0x0
BUS Width       x1
Reserved        0xa

$ sudo openFPGALoader -c ft231X --pins=RXD:RTS:TXD:CTS --fpga-part xc7a50t -f PicoEVB_demo.bit
empty
write to flash
Jtag probe limited to 3MHz
Jtag frequency : requested 6000000Hz -> real 3000000Hz
ret 0
Open file DONE
Parse file DONE
use: /usr/share/openFPGALoader/spiOverJtag_xc7a50t.bit.gz
load program
Load SRAM: [==================================================] 100.00%
Done
Shift IR d5
ir: 1 isc_done 1 isc_ena 0 init 1 done 0
Register raw value: 0x501079fc
CRC Error       No CRC error
Part Secured    0x0
MMCM lock       0x1
DCI match       0x1
EOS             0x1
GTS CFG B       0x1
GWE             0x1
GHIGH B         0x1
MODE            0x1
INIT Complete   0x1
INIT B          0x1
Release Done    0x1
Done            0x1
ID Error        No ID error
DEC Error       0x0
XADC Over temp  0x0
STARTUP State   0x4
Reserved        0x0
BUS Width       x1
Reserved        0xa
Detail:
Jedec ID          : 01
memory type       : 40
memory capacity   : 16
flash chip unknown: use basic protection detection
start addr: 00000000, end_addr: 00220000
Erasing: [==================================================] 100.00%
Done
Writing: [==================================================] 100.00%
Done

[trabucayre]

Look good but it's strange to have the done bit low. This is not expected.
I have to check the bitbanging mode to see if something is wrong.
I wait a bit before merging this PR due to this error

[trabucayre]

I have updated the ftdiJtagBitbang class with some fixes and updates. Could you re-try?
I can't test by myself since I haven't board based on artix without onboard cable.
Thanks

[umarcor]

The update fixed it:

$ sudo /opt/OFL/bin/openFPGALoader -c ft231X --pins=RXD:RTS:TXD:CTS ../../bits/PicoEVB_demo_101.bit
Jtag probe limited to 3MHz
Jtag frequency : requested 6000000Hz -> real 3000000Hz
Open file ../../bits/PicoEVB_demo_101.bit DONE
Parse file DONE
load program
Load SRAM: [==================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1

Note that the output ends there now. The content of STAT is not shown. I guess that change is intended?

[trabucayre]

Great! Thanks!
Yes, the STAT register is displayed when done is low.
So the ftdiJtagBitbang update fixes something wrong.

[trabucayre]

Applied.
Thanks @umarcor !

[umarcor]

Thanks for your quick attention. A pleasure, as always ;)