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build/altera: MAX 10: SDRInput as a fabric register (ALTDDIO_IN adds a clock of latency). - #2758
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…a clock of latency). ALTDDIO_IN's dataout_h is re-registered to line up with the falling-edge data, one clock more than SDRInput's contract (o = i registered once). On a DE10-Lite with LiteDRAM's HalfRateGENSDRPHY (166.67 MHz, CL3), the read data then landed a clock late: the BIOS memtest and the LiteDRAM BIST still passed (a round trip through one port, at the clock phases where the SDRAM samples commands and data on different edges), but data written by a native port (the BIST generator) and read through the CPU's L2 came back with the high half of every word lost. As a fabric register (packed in the IOE by FAST_INPUT_REGISTER): 0 of 1024 words differ, and the SDRAM clock phase window grows from 18 to 30 of 48 steps. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Follow-up to #2751/#2754 (MAX 10 IO lowering). #2754 kept
ALTDDIO_INforSDRInput, because a loopback showed it captures correctly in every bank. A loopback can't see latency, though.ALTDDIO_IN'sdataout_his re-registered to line up with the falling-edge data, which is one clock more thanSDRInput's contract (o=iregistered once). So on MAX 10SDRInputnow uses the same fabric-register fallback asSDROutput;FAST_INPUT_REGISTERpacks it into the IOE input register.What it broke, on a DE10-Lite (10M50, IS42S16320,
HalfRateGENSDRPHYat 166.67 MHz, CL3, Quartus 23.1):ALTDDIO_IN. Each is a round trip through one port, and with the read data a clock late, the SDRAM clock phase leveling (clock/intel, liblitedram: ALTPLL dynamic phase shift and SDRAM clock phase leveling at boot (SDR). #2756) still finds phases where round trips work.SDRInputas a fabric register: 0 of 1024 words differ. The leveling window also grows from 18 to 30 of 48 steps.Tested:
pytest test/build: 223 passed. The MAX 10 IO test now checks that neitherALTDDIO_OUTnorALTDDIO_INis emitted.common.py.Written by an AI agent (Claude Code), supervised by Florent Kermarrec.
🤖 Generated with Claude Code