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liblitedram: Keep the SDRAM clock phase check in the first MiB. - #2759
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…nts above survive a reboot). The check wrote strided words over the whole SDRAM at every boot, so a reboot destroyed data loaded above the BIOS's area (e.g. a model image uploaded over JTAG). SDRAM_CLK_PHASE_CHECK_SIZE (default 1 MiB) bounds it: still every bank and many rows. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Follow-up to #2756. The SDRAM clock phase leveling check wrote its strided words over the whole SDRAM at every boot. A reboot therefore destroyed data loaded above the BIOS's area (here, a 28 MB model image uploaded over JTAG at +4 MiB).
SDRAM_CLK_PHASE_CHECK_SIZE(default 1 MiB) now bounds the check's region. That still spans every bank and many rows; the BIOS memtest already uses the first 2 MiB.Caveat, from the board: this only makes the check's own writes non-destructive. During the scan the leveling crosses failing phases, where the SDRAM can mis-sample commands and refreshes, so contents elsewhere can still be hit. Loading data after the leveling is still the safe order. The change only stops the check from wiping the whole memory by design.
Tested on a DE10-Lite (10M50, IS42S16320 at 166.67 MHz CL3, HalfRateGENSDRPHY): BIOS leveling at boot as before (window 30 of 48 steps), memtest OK.
Written by an AI agent (Claude Code), supervised by Florent Kermarrec.
🤖 Generated with Claude Code